The present invention generally relates to the generation and distribution of clock signals to digital circuits, and more particularly to a sinewave clock distribution system having particular advantages in very high speed circuits.
Logic networks and digital transmission systems are designed to operate synchronously under control of a central clock. The clock signals are usually distributed in the digital network as pulses generated by a central pulse generator. A controlled impedance line matched at both ends must be used to prevent reflections which result in distortion of the clock pulse wave form. In any passive network, it is not possible to branch the controlled impedance line without impedance mismatch and/or without the use of a power dissipating impedance matching network. Instead of passive networks, it is known to use multiple output amplifiers for branching in the pulse distribution network; however, these amplifiers introduce additional delay in the clock pulse signal and, in addition, exhibit a temperature dependence in operation.
With the increased speed of digital logic circuits, the delay in the signal in interconnections and/or the precision of the timing of the clock ultimately determines the maximum bit rate of the whole system. Specifically, in very high speed circuits, the delays in the interconnecting signal lines are the same in magnitude as the delays in the logic circuits themselves. Therefore, at every individual point of the network, the clock timing must be adjusted to compensate for the line delays. Tapped lumped parameter delay lines are usually used for this purpose, but their disadvantages are cost, bulk, finite rise time, and delay adjustments only in discrete steps.